Memories are conventionally organized into matrices of storage cells. The cells of one and the same column are connected to one or more bit lines and are individually accessible by means of word lines. FIG. 1 provides a schematic view of a typical DRAM storage cell 2. This cell 2 comprises a selection transistor 4 and a storage capacitor 6.
In the example shown, the selection transistor 4 is an N channel MOS type transistor. Its control gate is connected to a word line WL and its drain is connected to a bit line BL. Its source is connected to a first terminal of the capacitor 6. This capacitor has a second terminal which receives a reference potential GND also called a ground potential. The storage cell enables the storage of a logic information element defined as a function of the voltage Vc present at the terminals of the capacitor 6, namely, in practice, as a function of the potential Vc (assuming that GND=0 V) of its first terminal.
It is generally possible to store two logic states, a high state and a low state, depending on whether the capacitor is charged or not. In the former case, the voltage Vc is, for example, equal to VCC, with VCC being a positive supply potential of the DRAM. In the latter case, Vc=GND.
Let it be assumed that the potential of the word line WL is smaller than or equal to the potential of the bit line BL. The selection transistor 4 is then off and the capacitor 6 is cut off from the bit line. To read the information stored in the cell 2, a precharging device is used to impose a reference potential Vref on the bit line. In general, the potential Vref is chosen so that it is intermediary between the values VCC and GND that can be assumed by the potential Vc. Typically, Vref is to be chosen to be equal to VCC/2. The bit line BL has a certain value of equivalent capacitance Cbl (represented in FIG. 1 by a parasitic capacitor 8) and stores the potential Vref by capacitive effect. Then, the cell 2 is selected, namely the transistor 4 is turned on by the application of an appropriate control potential to the word line WL. In practice, this selection will be made by taking the word line to the potential VCC.
A transfer of charges is then observed between the storage capacitor 6 and the parasitic capacitor 8 tending to make the voltages at the terminals of these two capacitors equal. The direction and scale of this transfer of charges are a function of the respective values of the capacitors 6 and 8 and of the voltages at their terminals. If the capacitance of the capacitor 6 is referenced Ccell and the initial voltage at its terminals is referenced Vc1, there is thus obtained at its terminals, after transfer of charges, a voltage Vc2 defined by the following relationship (assuming, to simplify matters, that the selection transistor does not cause a drop in voltage): EQU Vc2=(Cbl*Vref+Ccell*Vc1)/(Cbl+Ccell
If we assume that we have Vref=VCC/2 and Vc1=GND=0, then we obtain: EQU Vc2=Vc2(0)=(VCC/2)*[Ccell/(Cbl+Ccell)]
If we assume that Vc1=VCC, we obtain: EQU Vc2=Vc2(1)=(VCC/2)*[(Cbl+2* Ccell)/(Cbl+Ccell)]
In the former case, the transfer of charges is done from the bit line BL to the storage cell 2.
In the latter case, the transfer of charges is done from the storage cell 2 to the bit line BL. It is sufficient to use a comparator receiving Vc2 and Vref=VCC/2 (this potential VCC/2 being present for example on a bit line used as a reference) to obtain a logic read signal whose state represents the information initially stored in the cell 2.
If we write DV(0)=(VCC/2)-Vc2(0) and DV(1)=Vc2(1)-(VCC/2), we have DV(0)=DV(1)=DV=Ccell*(VCC/2)/(Ccell+Cbl).
Since the voltage at the terminals of the capacitor of the storage cell is modified when it is read, the reading of a cell includes a final step, known as a refresh step, to restore the initial voltage at the terminals of the storage capacitor. If this were not the case, the difference between the values of the potential Vc representing the logic states would tend to diminish, to the point of making the result of the read operation uncertain.
The DRAMs are generally associated with processors and used as buffer memories. An essential characteristic of these memories therefore is their speed. The reading will be faster for a lower value of the storage capacitor 6. Typically, capacitors with values in the range of about one-tenth of a picofarad are used. This magnitude raises a problem inasmuch as the variation in potential on the terminals of this capacitor by transfer of charges becomes lower as the value of the storage capacitor is reduced. To obtain a read signal which nevertheless can be interpreted and avoid reading errors, it is necessary to ensure a minimum potential difference between Vc2 and the reference potential VCC/2. It will be attempted, for example, to ensure Vc2(0)&lt;0.9*VCC/2 and Vc2(1)&gt;1.1*VCC/2. This represents a minimum margin of variation of the potential Vc2 plus or minus 10% with respect to the reference signal. This represents, for VCC=3 volts, a potential difference DV of 150 millivolts at the inputs of the comparator producing the read signal. This represents a practical lower limit.
It is furthermore preferable not to have an excessively large margin for the greater this margin, the lower the reading speed. Indeed, the duration needed for the transfer of charges between the bit line and the storage cell becomes smaller as the planned margin is made small. If it is assumed that the potential VCC is fixed, then a margin of plus or minus 10% entails an assumption, in practice, that Cbl=10* Ccell, namely about one picofarad.
One problem raised by DRAMs is, in practice, that of making a memory that is both fast and provides for a sufficient reading margin. The greater the capacity Cbl, the smaller is the variation of DV as a function of the state stored.
One approach is to increase the value of Ccell, thus making it possible to increase DV. However, this approach entails penalties for the memory in terms of speed. Furthermore, for a given technology, this requires the use of bulkier capacitors, which entails penalties in terms of integration. A transfer towards a smaller, minimum definition technology would, in addition, require a redefinition of the storage capacitors. Failing this, the simple transposition of a capacitor structure would result indeed in a reduction of the value of the capacitors and a reduced reading margin.
Another approach is to limit the value of Cbl. To do this, it is possible to limit the length of the bit lines and, therefore, the number of cells accessible per bit line. It is then necessary, if it is sought to obtain a large memory capacity, to greatly increase the number of bit lines. However, it is generally sought to limit the surface occupied by the circuits to minimize their costs and consumption.
Another approach to increasing the value of DV is to increase the value of the supply potential VCC. A problem then arises when it is sought to make circuits capable of working at low voltage, for example with VCC=3 volts or even less. The reduction of VCC indeed leads to a reduction of the reading margin.
If we assume that it is possible to find a technique by which it is possible to reconcile speed and sufficient reading margin, another problem arises if it is desired to increase the integration of the circuits by using a smaller minimum definition technology. Indeed, the threshold voltages of the transistors, and the offset voltages that result therefrom, tend to increase. As we have seen above, it is difficult to combine the speed of the memory with a sufficient reading margin. There is a risk, if the technology is changed, of having to modify the read comparator, and the read margin becomes excessively small in relation to the capacities of the comparator. This problem is also increased, as we have seen, because a simple transposition results in a reduction of the value of Ccell. This entails penalties in terms of reading margin for equivalent values of Cbl.